1. Field of the Invention
The present invention generally relates to a data strobe circuit, and more specifically, to an improved data strobe circuit for generating an internal strobe signal not by a data strobe signal applied externally but by a clock signal in a wafer test, thereby testing the larger number of chips at a wafer state simultaneously.
2. Description of the Prior Art
Recently, the main issue of the semiconductor memory field has been in a transition from integration to the operation speed. As a result, high speed synchronous memories such as a DDR SDRAM (Double Data Rate Synchronous DRAM) and a RAMBUS DRAM has been focused as a new issue in the semiconductor memory field.
The synchronous memory which refers to a memory operated synchronously with respect to an external system clock includes a SDRAM which leads the current mass production memory market of DRAMs. The SDRAM performs once data access at every clock by synchronizing input/output operations with respect to a rising edge of the clock. However, the high speed synchronous memory such as a DDR SDRAM performs twice data access at every clock by synchronizing input/output operations with respect to a falling edge as well as to a rising edge.
FIG. 1 is a circuit diagram illustrating a conventional data strobe circuit for generating an internal data strobe signal in a data input path.
The conventional data strobe circuit of FIG. 1 comprises comparators 101 and 102, NAND gates 103 and 104, and an AND gate 105. The comparator 101 compares a reference voltage VREF with a data strobe signal LDQS (or UDQS) applied externally. The comparator 102 compares the data strobe signal LDQS (or UDQS) with a signal LDQSB (or UDQSB) obtained by inverting the signal LDQS (or UDQS). The NAND gate 103 selectively outputs an output signal from the comparator 101 in response to an internal control signal EN_SGL. The NAND gate 104 selectively outputs an output signal from the comparator 102 in response to an internal control signal EN_DBL. The AND gate 105 performs an AND operation on output signals from the NAND gates 103 and 104, and outputs an internal strobe signal STROBE. Here, the data strobe signal LDQS(Low DQS) represents a signal having a predetermined low bit from the whole data strobe signals applied externally. The internal control signals EN_SGL and EN_DBL are to control generation of the internal strobe signal STROBE so that one of the output signals from the comparators 101 and 102 may be outputted as the internal strobe signal STROBE or the internal strobe signal STROBE is outputted by combination of the output signals.
The above-described conventional data strobe circuit requires external input signals such as the data strobe signals LDQS and LDASB applied externally for generation of the internal strobe signal STROBE for data latch.
However, when a large amount of memory devices are tested at a wafer state before the memory devices are packaged, the number of pins which can be tested simultaneously is determined by the physical restriction of measurement equipment. As a result, the large amount of chips cannot be tested at the same time due to the restriction of the number of pins in the conventional memory device which requires external input signals such as the data strobe signals LDQS and LDQSB and the reference voltage VREF to generate the internal strobe signal STROBE.